FIGS. 1 to 3 are views showing a method for manufacturing a symmetric semiconductor device.
Referring to FIG. 1, after forming an isolation area 11 on a semiconductor substrate 10 through a shallow trench isolation (STI) technology, an insulating layer 12 and a polysilicon layer 13 are stacked on the resultant structure. The semiconductor substrate 10 has areas for an N-type metal oxide semiconductor (NMOS) and a P-type MOS at one side and the other side thereof with respect to the isolation area 11.
As shown in FIG. 2, the insulating layer 12 and the polysilicon layer 13 are patterned to form gate insulating layers 12a and 12b and gate electrodes 13a and 13b respectively on the NMOS and PMOS area. Then, symmetric lightly doped drain (LDD) areas 14a and 14b are formed through respective ion implantation processes.
Thereafter, as shown in FIG. 3, after forming spacers 16a and 16b at sidewalls of the gate electrodes 13a and 13b, source and drain areas 15a and 15b are formed on the NMOS and PMOS areas through respective ion implantation processes.
However, problems in the structure of the symmetric semiconductor device are as follows.
First, a symmetric LDD structure having the same size at sides of each gate degrades a sub-threshold characteristic, reducing a driving current in a saturation state.
Second, in an inversion mode in which a sub-threshold current occurs, the LDD area at a source area degrades a swing characteristic of the device, and parasitic capacitance in an overlap area between the gate and the LDD area becomes a factor, reducing the operating speed of the device.
For example, when a flip-flop circuit is formed using the symmetric semiconductor device, an edge part of a swing characteristic graph cannot be not perpendicularly formed due to the influence of the driving current and the capacitance, so the swing characteristic graph has a parabolic configuration, representing propagation delay time.
Since the propagation delay time is proportional to the capacitance and inversely-proportional to an amount of driving current in each MOS area, the symmetric semiconductor device has a limitation in reducing the propagation delay time.
Third, a junction depth of an active area is important to control a critical dimension and an effective channel length of the gate electrode. Accordingly, the junction depth can be adjusted through an ion implantation process of indium (In) and/or antimony (Sb), which is are heavy ions, and a laser spike anneal process. In addition, the driving current may be reduced by forming a junction through a SiGe self aligned epitaxial growth scheme.
However, even if the junction depth is adjusted through the above method, short channel effects (SCEs) such as gate induced drain leakage (GIDL) and drain induced barrier lowering (DIBL), reverse short channel effects, and a problem of the parasitic capacitance still remain.
In addition, although the semiconductor device may be highly integrated, a driving voltage is relatively high, so electrons supplied from a source are excessively accelerated due to the potential gradient of the drain, a hot carrier instability phenomenon occurs in the vicinity of the drain, and the adjustment of a threshold voltage is very difficult.